1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having so-called SOI (silicon on insulator) structure.
2. Description of the Related Art
There are known conventional semiconductor devices having a substrate structure of the chip thereof based on so-called SOI structure. The SOI structure can be formed by techniques such as the SIMOX (separation by implanted oxygen) process including oxygen ion implantation and bonding process of silicon substrates, and is typically configured as exemplified by a chip 110 shown in FIGS. 8A and 8B, in which an insulating film 303 and a second Si substrate 302, as a single crystal semiconductor substrate, are layered in this order on a first Si substrate 301 as a support substrate.
The semiconductor device using the SOI structure (referred to as SOI semiconductor device, hereinafter) is preferably applicable to high-voltage-resistance applications. Similarly to the general semiconductor devices, the SOI semiconductor device is typically configured so that a chip thereof is mounted on an island of a package using a conductive adhesive or the like, and so that the external connection electrodes on the chip are respectively bonded to predetermined external terminals through wire bonding. Also the island is connected with any one of the external terminals (a grounding terminal in most cases), so that the support substrate in this case can be grounded through the island.
In response to demands for higher integration in the mounting, there are trends in adopting mounting methods or assembling methods, such as chip-on-board (referred to as COB, hereinafter) based on flip-chip technique and tape carrier package (referred to as TCP, hereinafter) also for the aforementioned SOI semiconductor devices, wherein, as typically shown in FIG. 8A, external connection electrodes (not shown) disposed on the second Si substrate 302 of the chip 110 are connected through bumps 201 to conductive interconnects 71 on a wiring substrate 70 on which the chip 110 is mounted, or, as typically shown in FIG. 8B, the external connection electrodes (not shown) disposed on the second Si substrate 302 of the chip 110 are connected to inner leads 80 of a TCP through the bumps 201. This, however, undesirably makes it difficult to apply potential to a first Si substrate 301.
The support substrate set at a floating potential raises a problem typically in that potential variation of the support substrate adversely affects operation of the device, in particular threshold potential, to thereby reduce operational margin of the device. It is also to be noted that voltage resistance of the device varies depending on potential of the support substrate, so that any variation in the potential of the support substrate during operation of the semiconductor device may cause malfunction of the device due to lowering in the voltage resistance thereof.
As one technique of avoiding floating potential of the support substrate, Patent Publication Laid-Open 2002-110950 typically discloses an exemplary SOI semiconductor device capable of applying potential from the surface of the device side to the support substrate.
FIG. 9 is a drawing for explaining the conventional semiconductor device disclosed in Patent Publication Laid-Open 2002-110950, and more specifically a schematic sectional view showing an essential portion of a chip owned by the semiconductor device. FIGS. 10A and FIG. 10B are enlarged views showing the portion “X” and portion “Y”, respectively, shown in FIG. 9. FIG. 11 is a perspective plan view schematically showing the chip. FIG. 9 shows a section taken along the line A-A′ in FIG. 11.
Referring now to FIG. 9 and so forth, the chip owned by the conventional semiconductor device comprises a P-type first silicon (Si) substrate 401 which serves as a support substrate and which has a specific resistance of, for example, 10Ω·cm and thickness of 650 μm, on which a silicon oxide film (referred to as “SiO2 film”, hereinafter) 409 of approximately 1 μm thick, as a first insulating film, and a P-type second Si substrate 403 having a specific resistance of 10Ω·cm and a thickness of 5 μm are layered in this order. In the chip the second Si substrate 403 has, formed therein, a plurality of device-forming regions 430 electrically isolated by isolation grooves 417. The chip also has substrate-contact-forming regions 405 having an area of 100 μm2 (10 μm×10 μm), as being disposed in appropriate vacant regions on the chip after removing the second Si substrate 403, and a plurality of external connection electrodes 440.
In each of the substrate-contact-forming region 405, there are provided, as shown in FIG. 10A in an enlarged manner, a TEOS oxide film 412 which is an insulating material film formed by using tetraethoxysilane (Si(OC2H5)4, referred to as “TEOS”, hereinafter) gas, and substrate contact holes 419 which penetrates the SiO2 film 409 and reaches contact regions 418 in the first Si substrate 401. The substrate contact holes 419 are filled with a metal as a conductive material, which is typified by tungsten (W) 406 to thereby configure contacts, and then the external connection electrodes 440 and the first Si substrate 401 are connected through a metal film interconnect, which serves as the support substrate connection wiring, typified by an aluminum (Al) interconnect 408. This makes it possible to apply a potential to the first Si substrate 401 from the external through the external connection electrode 440.
It is to be noted that substrate contact holes 419 in the example shown in FIG. 9 follow the multi-contact structure in which a plurality of minimum-dimension contact holes used in this chip (which are generally minimum-dimension contact holes used in the device-forming region 430) are arranged. Between the SiO2 film 409 and the TEOS oxide film 412, there are provided a field insulating film 410 and a SiO2 film 411.
The external connection electrode 440 is configured by removing a protective oxide film 413 and a protective nitride film 414 which cover the Al wiring 408, so as to form an opening having the Al interconnect 408 exposed therein, by forming thereon an adhesive metal film 415 such as a titanium (Ti) film, and further by forming a bump 407 typically composed of gold (Au). A predetermined region of the protective oxide film 413 has SOG (spin on glass) 416 coated thereon.
Elements necessary for realizing functions of the semiconductor device are formed on the top surface side of the individual device-forming regions 430 (on the surface side opposite to the junction surface with the SiO2 film 409). FIG. 9 and FIG. 10B show, as one example of such element, a field effect transistor (MOSFET, referred to as “MOS”, hereinafter) having a source diffusion layer 420, a drain diffusion layer 424, a gate electrode 423, a gate oxide film 421, and sidewall oxide films 422.
In the configuration enabling potential application to the support substrate (first Si substrate) as described in the above, the support substrate per se can be understood as one interconnect layer. It is therefore expected that use of the support substrate as one of interconnect layers for power source wiring, through which an extremely large current must be handled, makes it possible to correspondingly shrink an area necessary for forming the power source wiring on the surface of the single crystal semiconductor substrate (second Si substrate), and this is highly expectable for shrinkage in the chip size.
A problem, however, resides in that the support substrate (first Si substrate) per se, although having a conductivity, has a resistance larger than that of the aluminum interconnect formed on the surface of the single crystal semiconductor substrate (second Si substrate). Use of the support substrate in its intact form as the interconnect layer, therefore, results in that most portion of the current flows through the aluminum interconnect on the single crystal semiconductor substrate (second Si substrate) having a resistivity smaller than that of the support substrate (first Si substrate), rather than through the support substrate (first Si substrate), and this makes the support substrate less effective as the interconnect layer.
Another problem resides in that the support substrate (first Si substrate) in the conventional configuration is available only as a single kind of interconnect layer, because the entire portion of the support substrate is set to a single potential.